1. Field of the Invention
The present invention relates to a semiconductor device which in particular is used for improving the withstand voltage characteristics of a CMOS (Complimentary Metal Oxide Semiconductor) transistor circuit.
2. Background Information
Conventionally, CMOS transistor circuits are widely used in conventional semiconductor devices with integrated circuits (hereinafter to be referred to simply as semiconductor devices). A CMOS transistor circuit has a MOS transistor which forms a p-type channel in an operation (hereinafter referred to as a pMOS transistor), and a MOS transistor which forms an n-type channel in an operation (hereinafter referred to as an nMOS transistor). In this structure, a common control voltage is impressed to the gates of the pMOS transistor and nMOS transistor. The source of the pMOS transistor is connected to a power wiring LVDD to which an internal power supply voltage VDD will be impressed, and the source of the nMOS transistor is connected to a grounding wiring. Therefore, by connecting the drains of the pMOS transistor and the nMOS transistor with a common wiring, when a High level potential (e.g. the same level as the potential of the internal power supply voltage) is impressed to the gates of these transistors, for instance, the nMOS transistor is turned on while the pMOS transistor is turned off. Thereby, a Low level potential is outputted to the common wiring from the CMOS transistor circuit. On the other hand, when a Low level potential (e.g. the same level as the ground potential) is impressed to the gates of these transistors, for instance, the pMOS transistor is turned on while the nMOS transistor is turned off. Thereby, a High level potential is outputted to the common wiring from the CMOS transistor.
A commonly used semiconductor device comprising such CMOS transistor circuit mentioned above has a structure in which a gate is formed over a comparatively shallow doped layer while sandwiching a comparatively thin gate oxide in between, and thereby, high integration can be achieved. Therefore, in a commonly used semiconductor device having the structure mentioned above, one problem is that the device will easily break down due to a surge current when a static charge or the like is inputted externally. When using the CMOS transistor mentioned above, for instance, a surge current flows from the source of the pMOS transistor to the drain of the pMOS transistor when a static charge is inputted between the power wiring LVDD and the grounding wiring LGND. This surge current flows to the nMOS transistor from the pMOS transistor via the common wiring to which the drains of the pMOS transistor and the nMOS transistor are connected, and is discharged to the grounding wiring LGND via the nMOS transistor. At this time, if a withstand voltage of the nMOS transistor is insufficient, the nMOS transistor, particularly the drain thereof, may break down due to the surge current.
In order to protect a CMOS transistor from such surge current, in the conventional art, a protective circuit is connected in parallel to the CMOS transistor.
In this case, the protective circuit applies the surge current to itself by turning on before the surge current can flow into the CMOS transistor. For instance, a widely used HBM (Human Body Model) test suggests that a surge current with 1.33 A (ampere) can flow into the protective circuit when a static charge with 2 kV (kilo volt), which is a guaranteed value of a withstand voltage, is inputted to the CMOS transistor. By applying such comparatively large current to itself, the protective circuit can protect the CMOS transistor from the surge current.
As mentioned above, conventionally, when ensuring an ESD (electrostatic discharge) protection characteristic of a semiconductor device, a load current is concentrated at the protective circuit, or partially distributed to the protective circuit, in order to cover the weakness of a circuit that is an object of protection (i.e., a CMOS transistor in this case).
In addition, one problem is that, if a withstand voltage characteristic of the protective circuit is insufficient, the protective circuit itself may break down due to a surge current. Technology for coping with such problem is introduced in Japanese Laid-Open Patent Application No. 2002-324842 (hereinafter to be referred to as Patent Reference 1) for instance. In the technology according to Patent Reference 1, a bias voltage is impressed to a semiconductor on which a protective circuit having an nMOS transistor and a CMOS transistor circuit is formed. By this arrangement, a withstand voltage of the protective circuit can be improved.
Usually, in order to obtain higher highly integration, a CMOS transistor circuit comprises more than several hundred transistors even if small in size. At this time, it is desirable that pMOS transistors and nMOS transistors (hereinafter to be simply referred to as transistors when it is not necessary to distinguish between a pMOS transistor and an nMOS transistor) are designed to be as small as possible while ensuring a minimum required current driving ability for performance. By this arrangement, it becomes possible to miniaturize a chip size and reduce manufacturing costs while reducing a circuit forming area.
In the meantime, in order for the protective circuit to not be damaged by the surge current it bears by itself, the protective circuit has to be designed by applying particular design measurements in which measurements of portions relating to ESD protection characteristics become larger than the measurements of the transistors that construct the CMOS transistor circuit, while there are a number of design measurements which define the shapes of the transistors.
One of the design measurements that affects the ESD protection characteristic is the distance between the gate and the contact formed on the drain (hereinafter to be referred to as a gate-to-drain distance). For instance, if the gate-to-drain distance of the transistor constructing the CMOS transistor circuit is set to 0.4 μm (micrometer), a gate-to-drain distance of the transistor, particularly the nMOS transistor, constructing the protective circuit should normally be set to several times as large as a gate-to-drain distance of the transistor constructing the CMOS transistor circuit (e.g. 2.0 μm, which is five times as large). In this way, by designing the protective circuit such that the gate-to-drain distance of the transistor constructing the protective circuit is set large, it is possible to ease the damage that the transistor of the protective circuit might receive at the time when the static charge is inputted, and as a result, the withstand voltage characteristics of the protective circuit can be improved.
However, even when the protective circuit is connected in parallel to the CMOS transistor circuit as described above, the transistors constructing the CMOS transistor circuit are still left in a weaken state against a surge current that can be produced by the static charge etc. In this case, it is possible to have most of the surge current imposed on the protective circuit for the purpose of reducing the amount of current flowing to the CMOS transistor circuit. However, even with such arrangement, the problem of the surge current, the amount of which the protective circuit is unable to bear, flowing into the CMOS transistor circuit still remains.
In order to construct a CMOS transistor circuit such that it will not be damaged by a surge current flowing thereto, it is necessary to design it to be large in size, and to disperse the surge current evenly throughout the entire CMOS transistor circuit.
In order to disperse the surge current evenly throughout the entire CMOS transistor circuit, a ratio between a gate width of the pMOS transistor constructing the CMOS transistor circuit and a gate width of the nMOS transistor also constructing the CMOS transistor circuit has to be constant, and this applies to all the transistors constructing the CMOS transistor circuit.
FIG. 1 shows a circuit structure of a semiconductor device 800 including a buffer circuit 820 and an inverter circuit 910 as comparative example 1. The buffer circuit 820 is designed such that the ratio between the gate width of a pMOS transistor and the gate width of an nMOS transistor is constant. In FIG. 1, individual pMOS transistors qp2-qpn have the same gate width. Likewise, individual nMOS transistors qn2-qnn have the same gate width.
As shown in FIG. 1, when the pMOS transistors qp2-qpn and the nMOS transistors qn2-qnn having a constant gate width ratio between themselves are arranged in one-to-one correspondence, respectively, a surge current will be dispersed evenly on all of pMOS transistors qp2-qpn and the nMOS transistors qn2-qnn which are all connected in between a power wiring LVVD and a grounding wiring LGND. Therefore, with this structure, it is possible to improve the withstand voltage characteristics of the buffer circuit 820 which is a CMOS transistor circuit.
When the semiconductor device is constructed in this way, even if a comparatively small CMOS transistor circuit (e.g., a CMOS transistor circuit including a few to several dozen pMOS transistors and nMOS transistors (corresponding to the inverter circuit 910 in FIG. 1)) is formed together with a comparatively large CMOS transistor circuit (e.g., a CMOS transistor circuit including over a few hundred of pMOS transistors and nMOS transistors (corresponding to the buffer circuit 820 in FIG. 1)) between the same power wiring LVVD and grounding wiring LGND, a surge current will be distributed according to the size of the circuit, and therefore, the current density of each element will become constant. As a result, the semiconductor device 800 as a whole can obtain certain voltage withstand characteristics.
However, when a CMOS transistor circuit having transistors in which the gate width ratio is different from that of the transistors of other CMOS transistor circuits is connected together with the other CMOS transistor circuits between the same power wiring LVVD and grounding wiring LGND, there is a possibility that only the CMOS transistor circuit having the different gate width ratio will become easily damaged. This is because the surge current might be concentrated at the CMOS transistor circuit having the different gate width ratio.
Prior to explaining the reason why only the CMOS transistor circuit having the different gate width ratio will become easily damaged in the above-mentioned case where a CMOS transistor circuit having a different gate width ratio is connected together with other CMOS transistor circuits having the same gate width ratio between the same power wiring LVVD and grounding wiring LGND, an explanation will be given as to how the gate width ratio between a pMOS transistor and an nMOS transistor is normally determined in the design process.
Generally, a gate width ratio between a pMOS transistor and an nMOS transistor constructing a CMOS transistor circuit is set to 2:1. This is because there is a difference in mobility between an electron hole being a charge carrier in the pMOS transistor and an electron being a charge carrier in the nMOS transistor. That is, the mobility of the electron hole which is the charge carrier in the pMOS transistor is about half the mobility of the electron which is the charge carrier in the nMOS transistor. When an output potential of the CMOS transistor circuit is brought up to a level of internal power supply voltage VDD (e.g. 1.8V) from a ground level GND, the pMOS transistor functions as an active element, whereas the nMOS transistor functions as an active element when an output potential of the CMOS transistor circuit is brought down to the ground level GND (0V) from the level of internal power supply voltage VDD (e.g. 1.8V). Here, considering the nature of circuit operations, it is preferable that the time periods necessary for rising and decaying (here, ‘decaying’ is defined as a transition of level from H level to L level), respectively, are the same. While taking these factors into consideration, the gate width ratio between the pMOS transistor and the nMOS transistor is designed to be 2:1 in order to have approximately the same operation speed (i.e., the time period necessary for status transition) between the pMOS transistor and the nMOS transistor.
However, there are cases in which a gate width ratio of the pMOS transistor and the nMOS transistor constructing a CMOS transistor circuit is designed to be not necessarily constant. This is because, for instance, with respect to a CMOS transistor circuit in which a common control voltage is applied to a pMOS transistor and an nMOS transistor, a through current will flow into the CMOS transistor circuit when the transistors have the same operation speed. For example, when the common control voltage applied to a gate of each transistor is switched from a level of internal power supply voltage VDD to a ground level GND, the pMOS transistor will turn from ON to OFF while the nMOS transistor will turn from OFF to ON. At this time, there is a certain period of time in which the pMOS transistor and the nMOS transistor are both in ON, and the through current will flow from a power wiring LVVD to a grounding wiring LGND via the CMOS transistor circuit during this certain period of time.
Since such through current will increase power consumption in a semiconductor device including the CMOS transistor circuit, it is desirable that such through current is not generated, especially in electronic devices such as a cellular phone, where power saving is given priority. Particularly, when the gate width of both the pMOS transistor and the nMOS transistor constructing the CMOS transistor circuit is large, even if the period of time during which both the transistors would simultaneously be ON is very short, a considerable amount of through current would flow between the power wiring LVVD and the grounding wiring LGND. In such case, therefore, it is desirable that the through current is reduced as much as possible.
With respect to a method of reducing the through current, a method of decreasing the gate width of one of the pMOS transistor and the nMOS transistor constructing the CMOS transistor circuit is available, for example, either of which having less influence on circuit performance.
FIG. 2 shows a circuit structure of a semiconductor device 700 including a buffer circuit 720 and the inverter circuit 910, as comparative example 2. The buffer circuit 720 has an nMOS transistor having a decreased gate width. As shown in FIG. 2, the semiconductor device 700 has a modified structure of the semiconductor device 800 shown in FIG. 1 where the nMOS transistors qn2-qnn of the buffer circuit 820 are replaced with a single nMOS transistor qn2. This means that the semiconductor device 700 has a structure in which the total gate width of the nMOS transistors is decreased by eliminating the nMOS transistors qn3-qnn.
In this way, by decreasing the gate width of either transistor, the operation speed of this transistor will slow down, and thereby, it is possible to prevent through current from being generated due to the pMOS transistor and the nMOS transistor turning on simultaneously.
However, when reducing the gate width of the nMOS transistor as shown in FIG. 2, a surge current having passed through pMOS transistors qp2-qpn in the buffer circuit 720 will all flow into the nMOS transistor qn2, and this leads to a problem in which the nMOS transistor qn2, particularly the drain thereof (indicated as point k in FIG. 2) becomes damaged due to the surge current.
As can be seen from a semiconductor device 600 illustrated in FIG. 3 as comparative example 3, one method of resolving the problem mentioned above would be a method in which a dummy circuit 621 made up of a number of nMOS transistors (hereinafter to be referred to as dummy nMOS transistors) qn3-qnn, each of which gate is connected to a grounding wiring LGND via a resistance R1, i.e., each of which gate potential is fixed to a GND level, is connected in parallel to an nMOS transistor qn2, in place of the eliminated transistors (e.g., nMOS transistors qn3-qnn in the comparative example 2 shown in FIG. 2), for instance.
In the semiconductor device 600 shown in FIG. 3, a surge current flowing into the pMOS transistors qp2-qpn of the buffer circuit 720 as a whole will be dispersed on the dummy nMOS transistors qn3-qnn as well as the nMOS transistor qn2. As a result, the buffer circuit 720 will be able to have an improved withstand voltage characteristic.
However, in the above structure, the gate potential will not necessarily be the same between the nMOS transistor qn2 and the dummy nMOS transistors qn3-qnn in the buffer circuit 720. Therefore, there might be cases in which the surge current will not be dispersed evenly throughout the nMOS transistor qn2 and the dummy nMOS transistors qn3-qnn. As a result, particularly the nMOS transistor in the buffer circuit 720 may become damaged.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.